1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a fuse layout which provides an improved fuse blow process window.
2. Description of the Related Art
Memory capacity in very large scale integration (VLSI) semiconductor devices is always increasing. This is enabled in part by the continually decreasing size of individual elements. In conjunction with an increased density of components, an increase in the ratio of faulty components is produced. Chips which include any faulty elements are considered faulty, which reduces the production yield. To solve this problem, spare circuits or redundant circuits are manufactured within the chip to provide spare elements to be used to replace faulty elements. When a faulty element is detected during testing, the redundant circuits are used in place of the faulty circuits to increase the yield of the device. Faulty elements or circuits are disabled and redundant elements or circuits are enabled by blowing fuses formed in the semiconductor device.
Fuses are blown when a sufficient amount of energy is present to melt or break a connection between two points. Energy is most often deposited using lasers at a given point on the fuse. Conventionally, to prepare a laser breakable fuse used in a memory redundancy, a filament fuse made of polysilicon, molybdenum silicide, etc. is formed on an oxide layer as part of a wiring layer. The fuse is formed and an interlevel insulating layer and a protection layer are formed.
Referring to FIG. 1, a cross-sectional view of a polysilicon fuse structure is shown. Fuse structure 10 includes a substrate 12, for example a monocrystalline silicon substrate. A thermal oxide layer 14 is formed on substrate 12. A gate structure 16 includes a polysilicon layer 18 used for the fuse. Polysilicon layer 18 is covered by a tungsten silicide layer 20. Polysilicon layer 18 and tungsten silicide layer 20 are electrically isolated using a gate cap 22 on top of gate structure 16 and spacers 24 on lateral sides of gate structure 16. Gate cap 22 and spacers 24 are preferably formed from silicon nitride. An additional silicon nitride layer 26 is preferably deposited over gate structure 16. An interlevel dielectric layer 28 is then deposited over gate structure 16. Interlevel dielectric layer 28 may include borophosphosilicate glass (BPSG) which is polished prior to the deposition of a dielectric layer 30, which includes, for example, an oxide. Dielectric layer 30 is patterned for metal lines to be deposited in later leaving a thinned dielectric layer 31 over the fuse.
During operations, if a fuse is to be broken, an energy source such as a laser is applied to the fuse. A process window is a range of permissible energy below which a fuse will not blow and above which the structure experiences collateral damage. The process window is exceeded when too much heat is generated trying to blow a fuse. While applying a laser beam to the fuse, the temperature increases until the fuse breaks. However, since the dielectric material including gate cap 22, interlevel dielectric layer 28 and dielectric layer 30 are present over the fuse and function as a thermal barrier, temperatures may increase to a level which may damage surrounding structures including the substrate, thereby causing additional failures and reducing chip yield.
Therefore, a need exists for a method of increasing the process window for laser blown fuses. A further need exists for a method of incorporating a fuse structure with an improved process window into the existing semiconductor fabrication process.